Shimizu-Lab. Home Page
Department of Embedded Technology,
School of Information and
Telecommunication Engineering,
Tokai University, Japan.
Japanese
What's new:
- Demonstration of sfl2vl with Z80 compatible core and VGA is on
IP ARCH, Inc.
This design will fit into a Xilinx Spartan-3 Starter kit.
- coming soon: VAX11/780 instruction set compatible processor
- 15 Oct 2004: POP11/40 SFL source code is updated to v1.1.
- 05 Oct 2004: POP11/40 SFL source code is available.
See POP11 Page
- 03 Mar. 2004:
EDA Linux LiveCD based on SLAX is now available
download(4.0.1 base) [right click and save link] (about 300MB)
featuring: sfl2vl, sfl2vh, Icarus Verilog, Alliance VHDL, GTKwave, etc.
- 14 Jun. 2003: PDP11 compatible CPU POP11 Page created.
- 10 Aug. 2002:The Linux Super Page now supports Alpha, Sparc64 and IA32.
Feel free to download and to try it. Any comment will be welcome.
-
At 24 Jun. 2002(last update 26.Jul), we release the Linux Super Page for Alpha and Sparc64.
On Super Paged Alpha kernel, the matrix transpose benchmark runs
about 4 to 5 times faster than on the normal linux kernel.
-
At 19 Jun.2002, we tested super page for IA32, and got
1.9 times faster result on Celeron 900MHz with
a matrix transpose.
- (2-Aug-2002 updated)The alpha release of SFL to Verilog Converter
It includes mz80, m65, my88 files for test.
- PCB additional library
- Z80 compatible CPU alpha state.
- MCS6502 compatible CPU is available.
- 16bit small CPU (it will fit into an EPF10K10 CPLD).
SN/X is available.
In this page, you can also download 32bit CPU SN/K.
- i8080A instruction compatible processor
My80 is available.
- Linux Super Page Projects
- SCALT:Scalable Latency Tolerant Architecture.
This architecture is intended to extend software controlability
against long memory latency with a small buffer and
capability to issuing a lot of outstanding loads.
SCALT presentation
- The TRAJA 2.0 SFL source code is now
on the WEB.
This processor has most of JavaVM instruction set which was
1996 undergraduate thesis.
- The SP/1C is now on the project page which has a data cache and
hit under miss feature. This processor is still synthesizable, but it
may not fit in a ALTERA EPF10K10 (8700 asic gates are required).
- Pipeline processor SP/1 source code is published. See the project
page.
- Setting up English page.
Introduction.
Contact:
Prof. Naohiko Shimizu, Ph.D
Dept. Embedded Technology, School of Information and Telecommunication Engineering,
Tokai University
2-3-23 Takanawa, Minato-ku, Tokyo 108-8619
Japan
email : 
TEL:+81-3-3441-1171
SPAM mails should be transfered to
mailagain@nissankyo.jp
