Shimizu Lab./paper information

Domestic/International conference papers.

2003.4 - 2004.3
1. Ohyama, Shimizu, "IP: i8086 Instruction Comaptible Processor," Proceedings of IP Freemarket, The 11th FPGA/PLD Design Conference, pp.25-26, Yokohama, Jan., 2004
2. Shimizu, "Design Assist Tools: sfl2vl," Proceedings of IP Freemarket, The 11th FPGA/PLD Design Conference, pp.1-2, Yokohama, Jan., 2004
3. Ohyama, Shimizu, "Development of i8086 Instruction Comaptible Processor Core and LSI Development Environment with SFL," Proceedings of User Presentation, The 11th FPGA/PLD Design Conference, pp.35-41, Yokohama, Jan., 2004
4. Iida, Shimizu, "Design of POP-11(PDP-11 on Programmable Chip)," Proceedings of Asia and South Pacific Design Automation Conference 2004, pp.571-572, Yokohama, Jan., 2004
5. Shimizu, "Design of sfl2vl: SFL to Verilog Converter Based on an LR-Parser," IEICE Trans. Fundamentals, VOL.E86-A, No.12, pp.3225-3229, 2003
6. Shimizu, Kon, "Java Object Look Aside Buffer for Embedded Applications," MEDEA2003 Workshop held in Conjunction with the Twelfth International Conference on Parallel Architectures and Compilation Techniques, pp.43-49, Sep., 2003
7. Iida, Shimizu, "The Computer System Education with UNIX and PDP11," Information Technology Letters (Forum on Information Technology 2003), Vol.1 pp.43-44, Sep., 2003
8. Shimizu, "Logic Design Environment featuring SFL and Verilog," 5th Summer Workshop on Embedded System Technologies (SWEST5), pp.6-11, Jul., 2003
9. Nano, Oyama, Shimizu, "Design of USB 2.0 Device controller with fast request descrimination circuit," 5th Summer Workshop on Embedded System Technologies (SWEST5), pp.29-34, Jul., 2003
10. Koyama, Tanaka, Shimizu, "Design of Realtime Hardware MP3 Encoder," 5th Summer Workshop on Embedded System Technologies (SWEST5), pp.42-46, Jul., 2003
11. Iida, Shimizu, "PDP11/40 Compatible Processor for Embedded Systems," 5th Summer Workshop on Embedded System Technologies (SWEST5), pp.47-50, Jul., 2003
12. Hayasaka, Shimizu,"An Implementation and Evaluation of IA32 Linux Super Page," IPSJ Transactions on Advanced Computing Systems, Vol.44, No. SIG 10(ACS 2), Jul. 2003
13. Hayasaka, Shimizu,"Evaluation of Memory Performance by Linux Super Page and Page Coloring," Sympoosium on Advanced Computing Systems and Infrastructures, SACSIS2003, Vol.2003, No.8, pp.209-210, May. 2003
14. Iida, Shmizu," A PDP-11 Compatible 16-bit Embedded Processor Core For Programmable Chip," An International Symposium on Low-Power and High-Speed Chips COOL Chips VI, pp.79, Apr. 2003
15. Shimizu, "The Design of sfl2vl: SFL to Verilog Convertor Based on a LR-parser," Proceedings of the Workshop on Synthesis And System Integration of Mixed Information Technologies (SASIMI 2003), pp.251-257, Apr. 2003
16. Shimizu, "A transparent Linux super page kernel for Alpha, Sparc64 and IA32: reducing TLB misses of applications," ACM SIGARCH Computer Architecture News, Vol.31, Issue 1, pp.75-84, Mar. 2003
2002.4 - 2003.3
1. Kon, Shimizu, "Design of an i8080A Instruction Compatible Processor with Extended Memory Address ," Proceedings of ASP-DAC, pp.571-572, Jan. 2003
2. Kouyama, Nano, Kon, Shimizu, "Design of a USB Device Contoller IYOYOYO," Proceedings of ASP-DAC, pp.573-574, Jan. 2003
3. Hayasaka, Shimizu, "Design of a PCI Bus Interfarce," Proceedings of ASP-DAC, pp.579-580, Jan. 2003
4. Kouyama, Shimizu, "Non-Linear Quatization Algorithm suitable for Hardware MP3 Encoder," 10th FPGA/PLD Design Conference, pp. 23-29, Jan. 2003
5. Iida, Shimizu, "Design of a PDP11 Compatible CPU with Programmable Chip," 10th FPGA/PLD Design Conference, pp. 93-100, Jan. 2003
6. Nano, Kouyama, Kon, Shimizu, "Design of a USB Device Contoller which handle many of the protocol with hardware," 10th FPGA/PLD Design Conference, pp. 163-170, Jan. 2003
7. Hayasaka, Haramiishi, Shimizu, "PCI bus interfarce," IP Freemarket, 10th FPGA/PLD Design Conference, pp. 33-34, Jan. 2003
8. Hayasaka, Shimziu, "Implementation and Evaluation of Transparent Linux Super Page for IA32", IPSJ Computer System Symposium, Vol.2002, No.18, pp. 29-35, Nov. 2002
9. Shimizu, Takatori, "Linux Super Page Kernel for Alpha, Sparc64 and IA32 -- Reducing TLB misses of Applications," MEDEA-2002 : Workshop On Chip Multiprocessor: Processor Architecture and Memory Hierarchy Related Issues, Sep. 2002
10. Hayasaka, Shimizu, "GCC Porting Effort to a Minimum Instruction Set RISC," SWEST4, pp.98-103, Jul. 2002
11. Nano, Kouyama, Kon, Shimizu, "Design of a USB Device Contoller which handle many of the protocol with hardware," SWEST4, pp.15-18, Jul. 2002
12. Koyama, Shimziu, "A Design and Evaluation of MP3 Encoder on the Basis of Statistics Data of Sounds", IPSJ Computer System Symposium, Vol.2002, No.18, pp. 135-141, Nov. 2002
13. Li, Koyama, Shimziu, "An Optimization of MP3 Encoder for Faster Execution," IPSJ journal, Vol.43, No.6, pp. 1760--1768
14. Koyama, Li, Shimziu, "A Design and Evaluation of MP3 Encoder on the Basis of Statistics Data of Sounds", Proceeding of 15th Karuizawa Workshop on the circuit and systems, IEICE, pp.107-112, Apr. 2002
2001.4 - 2002.3
1. Kon, Shimizu, "Development of 8bit CP/M machine with Linux", Linux Conference Japan 2001
2. Shimizu, "Multi-Granuate TLB support for Linux and Performance Evaluation", Linux Conference Japan 2001
3. Lee, Kouyama, Shimizu, "Fast MP3 Encoder", Proceeding of Computer System Symposium, IPSJ Vol.2001, No.16, 137--143
4. Shimizu, ``Design of A Memory Latency Tolerant Processor(SCALT),'' MEDEA2001, 2001
2000.4 - 2001.3
1. Shimizu, ``Multi-Granularity Page Size Support for Linux and the Performance Evaluation,'' International Software Engineering Symposium (ISES01), Wuhan University Journal of Natural Sciences, Vol.6 No.1-2, 347--350, 2001
2. Mitake, Shimizu, "Design of the Latency Tolerant Processor(SCALT)", Proceedings of School of Engineering of Tokai University, Vol.40, No.1, 19--24, 2000
1999.4 - 2000.3
1. Shimizu, Naito, ``Design of JAVA processor -- TRAJA project,'' AP-ASIC99, 1999, The First IEEE Asia Pacific Conference on ASICs, 213--216
2. Shimizu, Mitake, ``Scalable Latency Tolerant Architecture(SCALT) and Its Evaluation,'' AP-ASIC99, 1999, The First IEEE Asia Pacific Conference on ASICs, 221--224
3. Shimizu, ``Processor Architecture and Evaluation for the Long Deviated Memory Latency,'' APPT99, 1999, Proceedings 3rd Workshop on Advanced Parallel Processing Technologies, 12--16
4. Mitake, Shimizu, "Design and the Evaluation of a Processor which corresponds to a deviated memory latency", Proceedings of School of Engineering of Tokai University, Vol.39, No.1, 43--48, 1999
1998.4 - 1999.3
1. Shimizu, "A Parallel Linear Equation Solver for Distributed Memory Parallel Processors, with Parallel Pipeline SOR method", Proceedings of School of Engineering of Tokai University, Vol.38, No.2, 1999
2. Shimizu, "JTAG Based On-board Logic Analyser for A Logic Evaluation Kit", ALTERA PLD World 98, 1998
3. Shimizu, "VLSI Design Education at Tokai University", 6th FPGA/PLD Conference, 1998
4. Shimizu, Noma, Tsuruta, "A Design of the FPGA Training System and the Seminar Courses for the VLSI Design at Tokai University", 12th PARTHENON users meeting, May. 14, 1998
  abstract
1997.4 - 1998.3
1. Funayama, Shimizu, "Realtime Video CNN simulator", 10th Karuizawa workshop on Circuit and Systems, Apr. 22, 1997
2. Shimizu, "Parallel PDE Solver with Pipelining Method of SOR", 2nd conference of JSCES, May. 1997
3. Watanabe,Shimizu, "High Performance Parallel FTT", 2nd conference of JSCES, May. 1997
4. Shimizu, Aoyagi, "Study on an implementation of JVM architecture", IPSJ SIG ARC-116, Jun. 27, 1997
  abstract
  slide(postscript)
5. Shimizu, "Parallel Pipelining SOR Method for a Iterative Linear Equation Solver on a Distributed Memory Parallel Processor", 11th Annual Symposium on High Performance Computer Systems, Manitoba, Canada, Jul., 1997
  abstract
  slide(postscript)
6. Shimizu, "Performance Evaluation on Scalable Latency Torelant Architecture", IPSJ SIG ARC (SWOPP 97), Aug., 1997
  abstract
  slide(postscript)
7. Shimizu, Watanabe, "High Performance Parallel FFT on Distributed Memory Parallel Computers", ISHPC'97, Fukuoka, Japan, Nov., 1997
8. Naitou, Shimizu, "Design of Pipeline Javachip by PARTHENON", The 11th PARTHENON users meeting, Dec., 1997
9. Shimizu, Yoshida, Noma, "A Note on the FPGA Training System and Course Design for the VLSI Design Seminar", Tech. report of IEICE, Vol. VLD97, No. 444, Dec., 1997
1996.4 - 1997.3
1. Shimizu, "NAS Parallel Benchmarks with Segmented / Switched Ethernet Connected Workstations", CTC-CSCC96, Korea, 1996 html (English)
2. Aoyagi, Kuroko, Enokida, Shimizu, "Design of The Java Virtual Machine Instruction Set Compatible Processor", The 9th PARTHENON meeting, Dec. 5, 1996, (Japanese)
3. Shimizu, "Pipelining Gauss-Seidel method as a PDE solver on a distributed memory parallel processor and a workstation cluster on an ethernet", Tech. Rep. of IEICE, COMP96-63, Jan. 23, 1997, (English)
  The program used in this report is here.
4. Shimizu, "Scalable Latency Torelant Architecture", IPSJ SIG Notes, Vol.97, No.21, pp.63-68, Mar. 6, 1997
- 1996.3
1. Shimizu, Tanaka, et. al, "Pipelining Gauss Sediel Method for Analysis of Discrete Time Cellular Neural Networks", IEICE Trans. Fundamentals, Vol E77-A-8, pp.1396-1403, 1994
2. Shimizu, Tanaka, "Some notes on a Relaxation Method for Circuit Simulations", NOLTA93, Hawai, 1993
3. Tanaka, Shimizu, "Pipelining System of Descrete Time Cellular Neural Networks for Information Coding and Decoding", ECCTD93, Swiss, 1993
4. Shimizu, Tanaka, "A Network-based Parallel Matrix Solver with Pipeling Gauss-Seidel Method", ECCTD93, Swiss, 1993
5. Tei, Shimizu, Tanaka, "Structural compression and reconstruction of static image by ideal diode retina network", ISCAS93, 1993
6. 田中,清水, "並列回路シミュレーション技術の動向と展望--ダイナミクスによる並列処理に向けて", 第6回回路とシステム軽井沢ワークショップ
7. Shimizu, Tanaka, "A Pipelining Gauss-Seidel Method for a Systolic Array", APCCAS92, Sidney, 1992
8. ... and more