The RISC technology is pushing the clocking rate up to 1GHz order. 
But comparing to the CPU clocking rate the improvement of memory 
latency is not so easy. Then for many numerical computations 
RISC could not offer sufficient performance, due to the heavy 
stalls for memory latency.  One approach to this problem is the 
register renaming combined with the out of order execution. 
Another approach is the pseudo vector architecture, which offeres
software visual registers and asyncronous transfer instructions.
They can provide more registers to wait for the memory latency.  But 
more and more latency will be, it requires more and more registers 
to wait. And it will be too complex for high speed RISC core to 
provide enough number of registers to cover the memory latency.
In this paper I present simple way for this problem.