SFL(Structured Function description Language) to Verilog/VHDL/LDF converter

History last updated 15 Sep. 2004

See LICENSE for use of this package.

The sfl2vl generates synthesizable verilog/VHDL/LDF file.


sfl2vl filename.sfl {-sim|-neg_clk|-neg_res|-sync_res|-d|-v|-icarus|-O}

-sim:      Generate simulation mode verilog files.
-O:        Optimize control signals
-neg_res:  Generate negative edge reset logic
-sync_res: Generate synchronous reset logic
-neg_clk:  Generate negative edge clock logic
-d:        Output debug information
-v:        print version information
-icarus:   Generate synthesizable code with Icarus Verilog

There are some difference between NTT's PARTHENON system and sfl2vl.

  1. sfl2vl does not allow users to use Verilog/SFL keywords as terminal name
  2. sfl2vl does not allow users to use conflict names between declare/module terminals, stage/task or state names.

The contents of the binary package is:
  1. sfl2vlbin.exe: The binary
  2. sflpp.exe: The pre-processor binary
  3. sfl2vl : The script to invoke sfl2vlbin.exe for Verilog conversion
  4. sfl2vh : The script to invoke sfl2vlbin.exe for VHDL conversion
  5. sfl2ldf : The script to invoke sfl2vlbin.exe for LDF conversion
  6. Makefile: See usage and package configuration in this file.
  7. HISTORY: update history

Binary Packages and Tutorials are placed on IP ARCH, Inc.

SFL sample designs:
  1. SN/X:16bit CPU.
  2. *mz80:Z80 semi-compatible (not yet compelete) CPU.

    mz80 main page was moved to sourceforge.jp

  3. *m65: 6502 compatible CPU
  4. PDP11 compatible CPU is available on POP11 Page.
* need full version to convert

The CPU files in the test suits are modified to meet sfl2vl naming style.