/******************************************

  Simple Pipeline Processor (SP/1) V1.0
  Synthesizable SFL source code.

  (C)Copyright by Naohiko Shimizu, 1998.   
  All rights are reserved.

  Contact information:
  Dr. Naohiko Shimizu
  School of Engineering, Tokai University
  1117 Kitakaname, Hiratsuka-city, Kanagawa, 259-1292, Japan
  email: nshimizu @ keyaki . cc .u-tokai.ac.jp
  URL: http://shimizu-lab.dt.u-tokai.ac.jp/

  The above URL is the primary distribution site for SP/1.
  You can get latest copy of sp1.sfl and patch information (if
  available).

  You can use full or part of this file for your project,
  if and only if the copyright notice is preserved on the
  every file and the every product which uses SP/1 or derivatives.

  You can synthesize this processor with PARTHENON.
  See the URL:
       http://www.kecl.ntt.co.jp/car/parthe
  for more information about PARTHENON.
  You also can down-load the Linux or FreeBSD or SUN version of
  PARTHENON from the URL:
       http://www.kecl.ntt.co.jp/car/parthe/html/package/
  
  *CAUTION*: Linux users may have to patch your kernel to synthesize
  larger SFL file because standard Linux kernel does not allow
  users to extend stack size any more than 8MB ;-p.
  Apply the linux.patch in this directory to patch your
	/usr/src/linux/asm/resource.h

  Features of the processor:
    Data 8bit, Instruction 16bit, Harvard architecture,
    8bit data/inst address spaces, load/store architecture,
    
    It has two types of instruction, i.e. R-type and I-type.

    R-type instructions  |OP|r2|r3|r1| - | ... r1 <- r2 op r3

    The instructions belong to the R-type are:

      ADD addition
      AND logical and
      SLT set less than (like MIPS architecture)
      NOT logical not
      SR  logical shift right by one
      RI  Return from interrupt   ex. ri

    I-type instructions  |OP|r1|r2| I | ... r1 <- r2(I)

    The instructions belong to the I-type are:

      LD  load from memory
      ST  store to memory
      LDA load address(or add immediate)
      BZ  branch on r1 is zero
      BAL branch and link
      IN  input from the IO port
      OUT output to the IO port

  There are four internal registers mapped on the IO space:
     ir0: Control and provide about interrupt and counter operations.
         <0>: interrupt mask
         <1>: counter run
         <6>: counter interruption occurred
         <7>: external interruption occurred
     ir1: The free run down counter. If the counter hit 0x00 and
         the interrupt mask is 0b1 then an interrupt will be occurred.
     ir2: The interrupt new PC.
     ir3: The interrupt old PC.

  Pipeline operations:
    5 stage pipeline IF|ID|EX|ME|WB
    Stall condition will be detected during the ID stage, and wait
    the resource availability within the stage. There are three 
    forwarding path within SP/1. You may stall up to 1 cycle for the
    I type instruction result. There also is a simple branch predicting
    mechanism for minimize the taken branch stall.

  C to SP/1 translation sample:

    ABI: 
       procedure return value : $1
       procedure argument (1st): $1
       procedure return address : $2
       frame pointer : in memory at 'sp'
       global pointer : in memory at 'gp'
       size of integer: 8bit

    Consider the following C code.

    int foo(int k) {
      if(k == 0) return(0);
      return(k+foo(k-1));
      }

    You can translate this code into the SP/1 assembler code like
    following:

         .entry foo
     foo:
         ld  $3,sp		; load frame pointer
         lda $3,-2($3)		; reserve two integers
         st  $3,sp		; update frame pointer
         st  $2,0($3)		; save return address
         st  $1,1($3)		; save local argument 'k'
         bz  $1,foo_1		; if 'k' is equal to 0, return
         lda $1,-1($1)		; make 'k-1'
         bal $2,foo		; call foo
         ld  $3,sp		; load frame pointer
         ld  $2,1($3)		; load local argument 'k'
         add $1,$1,$2		; calculate 'k+return value of foo'
     foo_1:
         ld  $2,0($3)		; load return address
         lda $3,2($3)		; calculate original frame pointer
         st  $3,sp		; update frame pointer
         bal $2,0($2)		; return from procedure
         .end


  Update informations:
    10-Dec-1998: More simple SN/1 released
    16-Nov-1998: Latest for SP/1
    19-Nov-1998: Latest for SP/1C
    22-Oct-1998: First public announcement.
******************************************/

FILES              ; The list of files
README            ; REAMDE file in English
README.jis   ; README file in Japanese ISO-2022jp

auto               ; Simulation script for SP/1 master file
f                      ; Simulation script
imem                ; Simulation script
intreq            ; Simulation script
px                    ; Simulation script
readall          ; Simulation script
rep                  ; Simulation script
autoc              ; Simulation script for SP/1C
readallc        ; Simulation script for SP/1C
repc                ; Simulation script for SP/1C
imemc              ; Simulation script for SP/1C

sn1.sfl         ; Non-pipelined SN/1 source code
sn1.edf         ; Synthesized EDIF code for ALTERA library

sp1.sfl         ; latest copy of SP/1 source code
sp1.edf         ; Synthesized EDIF code for ALTERA library

sp1c.sfl       ; latest copy of SP/1C source code
sp1c.edf       ; Synthesized EDIF code for ALTERA library
sp1c.ps         ; Synthesized logic diagram for ALTERA library

avaliable SP/1 files:
sp1-22Oct1998.sfl
sp1-26Oct1998.patch
sp1-26Oct1998.sfl
sp1-29Oct1998.patch
sp1-29Oct1998.sfl
sp1-05Nov1998.patch
sp1-05Nov1998.sfl
sp1-09Nov1998.patch
sp1-09Nov1998.sfl
sp1-12Nov1998.patch
sp1-12Nov1998.sfl
sp1-13Nov1998.patch
sp1-13Nov1998.sfl
sp1-15Nov1998.patch
sp1-15Nov1998.sfl
sp1-16Nov1998.patch
sp1-16Nov1998.sfl
sp1.edf
sp1.ps

avaliable SP/1C files:
sp1c-06Nov1998.sfl
sp1c-08Nov1998.patch
sp1c-08Nov1998.sfl
sp1c-13Nov1998.patch
sp1c-13Nov1998.sfl
sp1c-17Nov1998.patch
sp1c-17Nov1998.sfl
sp1c-18Nov1998.patch
sp1c-18Nov1998.sfl
sp1c-19Nov1998.patch
sp1c-19Nov1998.sfl
sp1c.edf
sp1c.ps