/* This file is a part of TRAJA(Tokai Research Approarch for JavaVM Architecture) project. Copyright 1997, 1998 Shimizu-Lab., School of Engineering, Tokai University. 1117 Kitakaname, Hiratsuka, Kanagawa, 259-1292, Japan email: nshimizu@et.u-tokai.ac.jp URL: http://shimizu-lab.et.u-tokai.ac.jp/ Though these files are RTL hardware source code, the copying policy just follow the GPL 2.0(see COPYING file). If you have any comment or improvement for these files, feel free to contact to me. */ /************************************************ * Javachip ALU * * Ver1.21 * ************************************************/ module javaalu { submod_type alu64 { input cry_on ; input inv_in2 ; input and ; input or ; input eor ; input cin ; input in1<64> ; input in2<64> ; output out<64> ; output vo ; output no ; output zo ; instrin do ; } input mode<3> ; input ci ; input a<64> ; input b<64> ; output out<64> ; output vo ; output no ; output zo ; instrin do ; alu64 ALU ; instr_arg ALU.do(cry_on,inv_in2,and,or,eor,cin,in1,in2) ; instruct do par { any { mode == 0b000 : out = ALU.do(0b1,0b1,0b0,0b0,0b1,^ci,a,b).out ; /* SBC */ mode == 0b001 : out = ALU.do(0b1,0b0,0b0,0b0,0b1,ci,a,b).out ; /* ADC */ mode == 0b010 : out = ALU.do(0b1,0b1,0b0,0b0,0b1,0b1,a,b).out ; /* SUB */ mode == 0b011 : out = ALU.do(0b1,0b0,0b0,0b0,0b1,0b0,a,b).out ; /* ADD */ mode == 0b100 : out = ALU.do(0b0,0b0,0b0,0b0,0b1,0b0,a,b).out ; /* EOR */ mode == 0b101 : out = ALU.do(0b0,0b0,0b0,0b1,0b0,0b0,a,b).out ; /* OR */ mode == 0b110 : out = ALU.do(0b0,0b0,0b1,0b0,0b0,0b0,a,b).out ; /* AND */ mode == 0b111 : out = ALU.do(0b1,0b1,0b0,0b0,0b1,0b1,a,b).out ; /* CMP */ } vo = ALU.vo ; no = ALU.no ; zo = ALU.zo ; } } module alu64 { submod_type alu16 { input cry_on ; input inv_in2 ; input and ; input or ; input eor ; input cin ; input in1<16> ; input in2<16> ; output out<16> ; output gout ; output pout ; output vo ; output zo ; instrin do ; } input cry_on ; input inv_in2 ; input and ; input or ; input eor ; input cin ; input in1<64> ; input in2<64> ; output out<64> ; output vo ; output no ; output zo ; sel cry<4> ; instrin do ; alu16 ALU3 ; alu16 ALU2 ; alu16 ALU1 ; alu16 ALU0 ; instr_arg ALU3.do(cry_on,inv_in2,and,or,eor,cin,in1,in2) ; instr_arg ALU2.do(cry_on,inv_in2,and,or,eor,cin,in1,in2) ; instr_arg ALU1.do(cry_on,inv_in2,and,or,eor,cin,in1,in2) ; instr_arg ALU0.do(cry_on,inv_in2,and,or,eor,cin,in1,in2) ; instruct do par { cry = ((cin&ALU0.pout&ALU1.pout&ALU2.pout) | (ALU0.gout&ALU1.pout&ALU2.pout) | (ALU1.gout&ALU2.pout) | ALU2.gout) || ((cin&ALU0.pout&ALU1.pout) | (ALU0.gout&ALU1.pout) | ALU1.gout) || ((cin&ALU0.pout) | ALU0.gout) || cin ; out = ALU3.do(cry_on,inv_in2,and,or,eor,cry<3>,in1<63:48>,in2<63:48>).out || ALU2.do(cry_on,inv_in2,and,or,eor,cry<2>,in1<47:32>,in2<47:32>).out || ALU1.do(cry_on,inv_in2,and,or,eor,cry<1>,in1<31:16>,in2<31:16>).out || ALU0.do(cry_on,inv_in2,and,or,eor,cry<0>,in1<15:00>,in2<15:00>).out ; vo = ALU3.vo ; no = out<63> ; zo = ALU0.zo&ALU1.zo&ALU2.zo&ALU3.zo ; } } module alu16 { submod_type alu4 { input cry_on ; input inv_in2 ; input and ; input or ; input eor ; input cin ; input in1<4> ; input in2<4> ; output out<4> ; output gout ; output pout ; output vo ; output zo ; instrin do ; } input cry_on ; input inv_in2 ; input and ; input or ; input eor ; input cin ; input in1<16> ; input in2<16> ; output out<16> ; output gout ; output pout ; output vo ; output zo ; sel cry<4> ; instrin do ; alu4 ALU43 ; alu4 ALU42 ; alu4 ALU41 ; alu4 ALU40 ; instr_arg ALU43.do(cry_on,inv_in2,and,or,eor,cin,in1,in2) ; instr_arg ALU42.do(cry_on,inv_in2,and,or,eor,cin,in1,in2) ; instr_arg ALU41.do(cry_on,inv_in2,and,or,eor,cin,in1,in2) ; instr_arg ALU40.do(cry_on,inv_in2,and,or,eor,cin,in1,in2) ; instruct do par { cry = ((cin&ALU40.pout&ALU41.pout&ALU42.pout) | (ALU40.gout&ALU41.pout&ALU42.pout) | (ALU41.gout&ALU42.pout) | ALU42.gout) || ((cin&ALU40.pout&ALU41.pout) | (ALU40.gout&ALU41.pout) | ALU41.gout) || ((cin&ALU40.pout) | ALU40.gout) || cin ; out = ALU43.do(cry_on,inv_in2,and,or,eor,cry<3>,in1<15:12>,in2<15:12>).out || ALU42.do(cry_on,inv_in2,and,or,eor,cry<2>,in1 <11:8>,in2 <11:8>).out || ALU41.do(cry_on,inv_in2,and,or,eor,cry<1>,in1 <7:4>,in2 <7:4>).out || ALU40.do(cry_on,inv_in2,and,or,eor,cry<0>,in1 <3:0>,in2 <3:0>).out ; gout = (ALU40.gout&ALU41.pout&ALU42.pout&ALU43.pout) | (ALU41.gout&ALU42.pout&ALU43.pout) | (ALU42.gout&ALU43.pout) | ALU43.gout ; pout = ALU40.pout&ALU41.pout&ALU42.pout&ALU43.pout ; vo = ALU43.vo ; zo = ALU40.zo&ALU41.zo&ALU42.zo&ALU43.zo ; } } module alu4 { input cry_on ; input inv_in2 ; input and ; input or ; input eor ; input cin ; input in1<4> ; input in2<4> ; output out<4> ; output gout ; output pout ; output vo ; output zo ; sel tmp_in2<4> ; sel g<4> ; sel p<4> ; sel data<4> ; sel cry<4> ; sel cout ; instrin do ; instruct do par { any { inv_in2 : tmp_in2 = ^in2<3> || ^in2<2> || ^in2<1> || ^in2<0> ; else : tmp_in2 = in2 ; } g = (in1<3> & tmp_in2<3>) || (in1<2> & tmp_in2<2>) || (in1<1> & tmp_in2<1>) || (in1<0> & tmp_in2<0>) ; p = (in1<3> | tmp_in2<3>) || (in1<2> | tmp_in2<2>) || (in1<1> | tmp_in2<1>) || (in1<0> | tmp_in2<0>) ; data = ((p<3> & or) | (g<3> & and) | (p<3> & ^g<3> & eor)) || ((p<2> & or) | (g<2> & and) | (p<2> & ^g<2> & eor)) || ((p<1> & or) | (g<1> & and) | (p<1> & ^g<1> & eor)) || ((p<0> & or) | (g<0> & and) | (p<0> & ^g<0> & eor)) ; cry = (((cin&p<0>&p<1>&p<2>) | (g<0>&p<1>&p<2>) | (g<1>&p<2>) | g<2>) & cry_on) || (((cin&p<0>&p<1>) | (g<0>&p<1>) | g<1>) & cry_on) || (((cin&p<0>) | g<0>) & cry_on) || (cin & cry_on) ; cout = (cin&p<0>&p<1>&p<2>&p<3>) | (g<0>&p<1>&p<2>&p<3>) | (g<1>&p<2>&p<3>) | (g<2>&p<3>) | g<3> ; out = data @ cry ; gout = (g<0>&p<1>&p<2>&p<3>) | (g<1>&p<2>&p<3>) | (g<2>&p<3>) | g<3> ; pout = p<0>&p<1>&p<2>&p<3> ; vo = cout @ cry<3> ; zo = ^(out<3> | out<2> | out<1> | out<0>) ; } }