/* This file is a part of TRAJA(Tokai Research Approarch for JavaVM Architecture) project. Copyright 1997, 1998 Shimizu-Lab., School of Engineering, Tokai University. 1117 Kitakaname, Hiratsuka, Kanagawa, 259-1292, Japan email: nshimizu@et.u-tokai.ac.jp URL: http://shimizu-lab.et.u-tokai.ac.jp/ Though these files are RTL hardware source code, the copying policy just follow the GPL 2.0(see COPYING file). If you have any comment or improvement for these files, feel free to contact to me. */ /************************************************ * TRAJA 2.0 64 bit shifter * *Ver1.0 * * **********************************************/ module shift64 { submod_type shift_64 { input sftl_r ; input sign ; input x<6> ; input in<64> ; output out<64> ; instrin do ; } input in<64> ; input x<6> ; output out<64> ; instrin sll ; instrin srl ; instrin sra ; shift_64 shift64 ; instr_arg shift64.do(sftl_r,sign,x,in) ; instruct sll out = shift64.do(0b1,0b0,x,in).out ; instruct srl out = shift64.do(0b0,0b0,x,in).out ; instruct sra out = shift64.do(0b0,0b1,x,in).out ; } module shift_64 { input sftl_r ; input sign ; input x<6> ; input in<64> ; output out<64> ; sel msb ; sel tmp5<64>, tmp4<64>, tmp3<64>, tmp2<64>, tmp1<64> ; instrin do ; instrself sftl32, sftr32, pass32 ; instrself sftl16, sftr16, pass16 ; instrself sftl8 , sftr8 , pass8 ; instrself sftl4 , sftr4 , pass4 ; instrself sftl2 , sftr2 , pass2 ; instrself sftl1 , sftr1 , pass1 ; instruct do par { msb = in<63> & sign ; any { sftl_r : par { any { x<5> : sftl32() ; else : pass32() ; } any { x<4> : sftl16() ; else : pass16() ; } any { x<3> : sftl8() ; else : pass8() ; } any { x<2> : sftl4() ; else : pass4() ; } any { x<1> : sftl2() ; else : pass2() ; } any { x<0> : sftl1() ; else : pass1() ; } } else : par { any { x<5> : sftr32() ; else : pass32() ; } any { x<4> : sftr16() ; else : pass16() ; } any { x<3> : sftr8() ; else : pass8() ; } any { x<2> : sftr4() ; else : pass4() ; } any { x<1> : sftr2() ; else : pass2() ; } any { x<0> : sftr1() ; else : pass1() ; } } } } instruct sftl32 out = tmp5<31:0> || 0b00000000000000000000000000000000 ; instruct sftr32 out = msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || tmp5<63:32> ; instruct pass32 out = tmp5 ; instruct sftl16 tmp5 = tmp4<47:0> || 0b0000000000000000 ; instruct sftr16 tmp5 = msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || msb || tmp4<63:16> ; instruct pass16 tmp5 = tmp4 ; instruct sftl8 tmp4 = tmp3<55:0> || 0b00000000 ; instruct sftr8 tmp4 = msb || msb || msb || msb || msb || msb || msb || msb || tmp3<63:8> ; instruct pass8 tmp4 = tmp3 ; instruct sftl4 tmp3 = tmp2<59:0> || 0b0000 ; instruct sftr4 tmp3 = msb || msb || msb || msb || tmp2<63:4> ; instruct pass4 tmp3 = tmp2 ; instruct sftl2 tmp2 = tmp1<61:0> || 0b00 ; instruct sftr2 tmp2 = msb || msb || tmp1<63:2> ; instruct pass2 tmp2 = tmp1 ; instruct sftl1 tmp1 = in<62:0> || 0b0 ; instruct sftr1 tmp1 = msb || in<63:1> ; instruct pass1 tmp1 = in ; }