POP11 is a PDP11 compatible processor fit into an FPGA.
Design language is SFL and we converted SFL to Verilog with
We have two version of POP11.
This processor is PDP11/40 compatible with MMU and EIS as well as
serial I/O, IDE hard drive interface and timer.
It can boot UNIX from IDE HDD.
It uses about 3000 logic cells with Altera FPGA.
We are currently use Cyclone EP1C3 or FLEX EP1K100 in our lab.
See AUN SeedNet Poster or Pictures
SFL source code of POP11/40 is available.
See COPYING to use of this package.
This processor is PDP11/40 compatible without MMU/EIS. It can fit within Altera's EPF10K30E. Configuration file for CQ publishers FLEX evaluation kit is provided on CDROM of Design Wave magazine, No.7, July. 2003.
Contact:Prof. Naohiko Shimizu
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