Shimizu Lab. Research/Educational Projects.
- COMPUTER ARCHITECTURE
- sfl2vl an HDL Converter(SFL to Verilog)
- POP11(PDP-11 compatible processor On Programmable chip) is now
running 'proc' and booting 'unix'.
- Gcc3.2 patch
to make PDP/11 port compilable
- Z80 compatible CPU alpha state.
- MCS6502 compatible CPU is available.
- i8080A compatible CPU is available.
- Linux Super Page project
- SCALT:Scalable Latency Tolerant Architecture.
This architecture is intended to extend software controlability
against long memory latency.
- TRAJA:Tokai Reseach Approach for JVM Architecture.
Constructing High Performance Java processor with PARTHENON(TM) HDL.
See the project home page,
for more information and TRAJA2.0 source/block diagram.
We have TRAJA3.0 code, but it is not synthesizable yet.
- SP/1: Simple pipeline processor with forwarding and branch
prediction designed for undergraduate education.
See this page for more information .
The directory also contains a SP/1C processor which has a small data
cache for advanced students.
- PC/WS CLUSTERS
- Parallel-P4 connection.
Multiple ethernet connected PC/WS clusters are are under the development.
- High performance computing
- High Performance FFT for Parallel Processors.
- Parallel Pipelining SOR Method(ppSOR).
- High performance DGEMM code by C.
This program will mark high performance only if the system is well
designed with the memory subsystem.
see the page
- STRIDE STREAM BENCHMARK