Shimizu Lab./Projects

Shimizu Lab. Research/Educational Projects.

COMPUTER ARCHITECTURE
1. sfl2vl an HDL Converter(SFL to Verilog)
2. POP11(PDP-11 compatible processor On Programmable chip) is now running 'proc' and booting 'unix'.
3. Gcc3.2 patch to make PDP/11 port compilable
4. Z80 compatible CPU alpha state.
5. MCS6502 compatible CPU is available.
6. i8080A compatible CPU is available.
7. Linux Super Page project
8. SCALT:Scalable Latency Tolerant Architecture.
  This architecture is intended to extend software controlability against long memory latency.
  SCALT presentation
9. TRAJA:Tokai Reseach Approach for JVM Architecture.
  Constructing High Performance Java processor with PARTHENON(TM) HDL.
  See the project home page, for more information and TRAJA2.0 source/block diagram. We have TRAJA3.0 code, but it is not synthesizable yet.
10. SP/1: Simple pipeline processor with forwarding and branch prediction designed for undergraduate education.
  See this page for more information . The directory also contains a SP/1C processor which has a small data cache for advanced students.
  - latest SP/1 source code
  - SP/1 Synthesized EDIF code for ALTERA
  - latest SP/1C source code
  - SP/1C Synthesized EDIF code for ALTERA
  - SN/X 16bit simple processor for architecture education see the page
    or see the japanese page
PC/WS CLUSTERS
1. Parallel-P4 connection.
  Multiple ethernet connected PC/WS clusters are are under the development.
High performance computing
1. High Performance FFT for Parallel Processors.
2. Parallel Pipelining SOR Method(ppSOR). Example here.
3. High performance DGEMM code by C. This program will mark high performance only if the system is well designed with the memory subsystem. see the page
4. STRIDE STREAM BENCHMARK